Engineering & Research Portfolio

Silicon → Systems
High-Speed Interface

// Tony C. Chen · CFA Candidate · IC Packaging Engineer

PCIe 5.0 High-Speed CFA Candidate Quant Research
Contact → View Portfolio

Monday, March 16, 2026

Engineering & Research Portfolio

18 Years.
Silicon → Systems
Package → Portfolio.

// Tony C. Chen · CFA Candidate · IC Packaging Engineer · Quantitative Researcher

從封裝工程到量化研究——同一套方法論，兩個世界的護城河 · 台灣

18
Years in Industry
6
Companies / Roles
CFA
Candidate
10+
Yrs Quant Trading
iPhone
3GS Package Shipped
USB-C
DP-Alt Mode Launched
Active: PCIe 5.0 Retimer FCBGA · CoWoS · Chiplet FEM · SPC · JEDEC Qual CFA Candidate · Quant Backtest · R/Python DFM · NPI · OSAT Management AI Infrastructure · LLM Ops
Pitch an Opportunity → APM Matrix ↗ View Full Career ↓
00 // The Engineering Thesis 核心論點

I started my career in 2007 doing something few engineers ever do: drafting design rules from scratch for new substrate processes at a company that would later become a Leading Substrate Vendor. That first role taught me something that has defined every job since: quality is not engineered in, it is managed in.

Over 18 years across six companies — including a Global Substrate Vendor, a Leading OSAT, and multiple Tier-1 Design Houses — I have shipped packages for Top Smartphone Brands, launched USB 3.1 Type-C DP-Alt mode into the market, owned RMA resolution programs for Tier-1 customers, and built DFM process-control frameworks from the assembly floor up. Along the way I noticed something: the statistics I used to control a plating bath and the statistics I needed to manage a trading position were the same equations.

TonyCapm.com is where those two disciplines converge. Statistical process control thinking applied to market drawdowns. Process capability translated into portfolio risk budgets. High-fidelity physics models running on proprietary infrastructure that backtests market trend-following strategies. This is not a pivot. It is the same system, run on a different substrate.

Tony C. Chen · CFA Candidate · Taipei, Taiwan 18 yrs semiconductor · 10+ yrs quant research
2007 – 2017 · FOUNDATION
Process & Package Engineering
Built deep substrate and IC packaging competency across a Leading Substrate Vendor, Global OSAT, and Tier-1 Design House. Shipped into Top Smartphone Brands. Launched USB3 family to market. Developed OSAT management and NPI workflows.
2017 – 2021 · EXPANSION
Customer-Facing Engineering Leadership
Moved to customer-application and quality engineering roles at multiple Tier-1 Design Houses — translating internal engineering language into customer outcomes. RMA ownership, PCN coordination, FA coordination, audit management.
2021 – PRESENT · CONVERGENCE
AI Startup + Independent Research
Package & Customer Quality Engineer at AI semiconductor startup. Working on PCIe 5.0 High-Speed Retimer assembly and process control. Simultaneously running independent quant research lab — applying semiconductor QA methodology to financial time-series data. CFA Candidate.
01 // Career Timeline 職涯時間軸
May 2025
Present
Active
TonyCapm · Self-Employed · Remote
Taipei, Taiwan
Quantitative Researcher
  • System Architecture: Deployed scalable virtualization and sentiment pipelines. Built secure internal network tunneling across proprietary edge infrastructure.
  • Algorithm Development: Engineered quant strategies. BTC Fast Trend: 48.2% annualized, Sharpe 1.85.
  • Data Engineering: Adapting engineering process control methodology to financial time-series.
R · Python Docker · Linux SPC → Finance
Oct 2021
Apr 2025
3 yrs 7 mos
AI Semiconductor Startup
Package & Customer Quality Engineer
  • Authority in assembly process control plans and DFM philosophy for High-Speed PCIe 5.0 Interface.
  • Owned substrate design inputs and OSAT QMS maintenance.
  • Owned end-to-end customer RMA resolution and 8D reporting.
DFM OSAT Management 8D / CAPA
Feb 2019
Jul 2020
1 yr 6 mos
Global Semiconductor Leader
Taipei City, Taiwan
APM, Account Manager
  • Coordinated Product Change Notifications (PCN) for zero-surprise transitions.
  • Coordinated Failure Analysis (FA) on RMA cases for key accounts.
PCN Mgmt Customer Quality
Jun 2017
Jan 2019
1 yr 8 mos
Tier-1 Human Interface Design House
Customer Application / IC Packaging Engineer
  • Led NPI activities for automotive and consumer electronics packaging.
  • Translated customer requirements into package design constraints.
NPI Automotive Qual
Feb 2011
Jun 2017
6 yrs 5 mos
Leading USB Connectivity Design House
Package Engineer
  • Launched USB 3.0/3.1, Type-C DP-Alt mode, and AOC packages.
  • Led OSAT management through NPI, process control, and yield ramp.
★ Achievement: Successfully established the foundation for the Design House's USB3 packaging portfolio.
Jul 2009
Feb 2011
1 yr 8 mos
Leading Global OSAT
Product Engineer
★ Achievement: Introduced 8-die stack package to mass production for Tier-1 Smartphone Brand.
02 // Proprietary Physics Study 有限元素模擬研究
⚠   SELECTED PARAMETERS REDACTED — REPRESENTATIVE OF DEVICE CLASS
Advanced SMT Package — Reliability Assessment
SOLVER: HIGH-FIDELITY MECHANICAL SOLVER · MESH: ~1.2M ELEMENTS · TC PROFILE: JEDEC-A104
64.86 µm
Peak Warpage
⚠ +29.7% vs Limit
1,960
Fatigue Cycles
⛔ −2% vs Target
0.18°C/W
Thermal Resistance
✓ Within Spec
4.2 ppm/°C
CTE Mismatch
▶ Acceptable
⚠ FINDING 01 · WARPAGE
Peak warpage 64.86 µm exceeds JEDEC limit (50 µm). Fix: Increase substrate core thickness.
⛔ FINDING 02 · FATIGUE
Predicted 1,960 cycles vs 2,000 floor. Corrective action required pre prototype.
03 // Skills Matrix 技能矩陣
Engineering
IC Packaging96%
Process Quality97%
Physics Simulation83%
Quantitative
R / quantmod91%
Risk Sizing88%
CFA Theory86%
Tech / Infrastructure
Virtualization / OS83%
AI Systems Mgt78%
04 // The Opportunity 機會投遞
What I Bring
⬡
Full-Stack Packaging Depth
From substrate design to OSAT management (Tier-1 Accounts) and AI chiplet packaging.
◈
Rare Domain Convergence
Professional who runs high-fidelity physics models. Bridging engineering precision with market probability.
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Monday, January 26, 2026

Financial Trading Strategies

Quantitative models designed for volatility targeting and regime-based asset rotation.

⚙ Live Simulation

AI Arena: The Construct

Enter the simulation. Test your own parameters against the advancing probability matrix in real-time.

Launch AI Arena →
▲ Trend Following

BTC Fast Trend (EMA 50)

A high-frequency trend following strategy optimized for Crypto assets. It uses a shorter 50-day Exponential Moving Average (EMA) for faster entry signals and targets 50% annualized volatility.

  • Risk Control: Dynamic position sizing based on rolling volatility.
  • Signal: 50-day EMA crossover (Aggressive).
  • Benchmark: Outperforms Buy-and-Hold SPY in backtests.
✓ 5-Year Backtest Results
Annualized Return
48.2%
+15% vs Benchmark
Sharpe Ratio
1.85
Max Drawdown
-22.4%
Recovery Factor
2.15
## 5-Year Backtest: FAST Trend (EMA 50)
symbol_asset <- "BTC-USD"
lookback_trend <- 50  # Fast entry
target_vol     <- 0.50 # Aggr. Target

# Signal Calculation
trend_line <- EMA(prices$Asset, n = lookback_trend)
trend_signal <- ifelse(prices$Asset > trend_line, 1, 0)

# Volatility Weighting
vol_weight <- target_vol / rolling_vol
final_weight <- lag(trend_signal * vol_weight, 1)

charts.PerformanceSummary(comparison)
🔒

Proprietary Algorithm

Core logic reserved for clients.

Unlock Full Strategy
🛡 Regime Switching

Risk-On / Risk-Off Rotation

A macro-defensive strategy that rotates between Growth (SPY) and Defensive/Consumer Staples (KXI) sectors based on the 200-day Moving Average regime signal.

  • Mechanism: Switches to KXI (Staples) when SPY falls below 200-day MA.
  • Goal: Preserves capital during bear markets while capturing bull runs.
  • Execution: Daily signal check with 1-day lag.
✓ Performance Metrics
Annualized Return
12.8%
Consistent Growth
Volatility
9.2%
Low Risk
Win Rate
64%
Sortino Ratio
1.4
# Risk-On/Risk-Off Rotation (SPY vs KXI)
# 1. Define Regime Signal
spy_sma200 <- SMA(prices$SPY, n = 200)

# Lag signal to avoid look-ahead bias
regime <- Lag(ifelse(prices$SPY > spy_sma200, 1, 0))

# 2. Execute Strategy (The Switch)
# If Signal == 1 (Bull), Return = SPY Return
# If Signal == 0 (Bear), Return = KXI Return
strat_ret <- (regime * asset_returns$SPY) + 
             ((1 - regime) * asset_returns$KXI)

# 3. Compare
comparison <- merge(strat_ret, bench_ret)
🔒

Proprietary Algorithm

Core logic reserved for clients.

Quant Trading with a QA Manager's Mind

Every trade is a "Lot." Every market shock is a "Process Variation." Using GPAT/DPAT principles from semiconductor manufacturing, this framework treats a 1.47 Net Calmar not as a goal, but as a statistical requirement for system-level stability.

Process Precision
98.83% Yield

First Pass Yield (FPY)

Stability Spec
Cpk 0.97

Industry-Standard Capability

SYSTEM_LABEL: FINAL_EQUITY_SUMMARY
ANALYTICS: OUTLIER_DETECTION_MODEL
Sigma Outlier Detection

Identifying 17 Outliers for Root Cause Analysis (RCA)

MODEL_OUTPUT: RISK_PROFILE_HEATMAP
Risk Heatmap

Core algorithm logic is proprietary.

Contact to Unlock Full Strategy
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